1. Field of the Invention
The present invention relates to a bus wiring formed on a printed circuit board.
2. Description of the Related Art
A higher speed in operations and a higher density of wirings are demanded for a printed circuit board along with sophistication of electronics devices in recent years. For that reason, a bus wiring is frequently used in which plural signal lines through which a signal can be transmitted at a high speed are arranged in parallel. In a case where the signals are transmitted by using the bus wiring from a transmission-side semiconductor package to a reception-side semiconductor package, lengths of respective wirings are set to be equal to each other. If a large difference exists in the lengths of the respective wirings, an operational timing of the reception-side semiconductor package is deviated, and noise is increased because of a difference in the timing at which the signals are reflected at connection points of the respective wirings.
In a case where the transmission-side semiconductor package is mounted on one of surfaces of a multi-layered printed wiring board and the reception-side semiconductor package is mounted on the other surface, the bus wiring is arranged by using via holes. A ground layer or a power supply layer is generally formed on an inter layer of the multi-layered printed wiring board, and the ground layer or the power supply layer serves as a return path for the signal flowing through the signal wiring such as the bus wiring.
The via holes are prepared also in the ground layer or the power supply layer in the case of the above-described multi-layered printed wiring board. To design the printed wiring board at a high density in recent years, the bus wirings are arranged to be adjacent to each other as much as possible. For that reasons, the via holes are also arranged to be adjacent to each other. However, if the via holes prepared in the ground layer or the power supply layer are continuously arranged, the return path for the signal is divided by the via holes. Thus, radiation noise is increased.
Japanese Patent Laid-Open No. 8-340161 discloses a configuration in which the via holes are prepared in a diagonal manner, or a wider interval is designed every two or four via holes in a case where the bus wirings are formed on the multi-layered printed wiring board. The return path is secured by preparing the via holes in the above-described manner.
In recent years, a semiconductor package of a ball grid array (BGA) type is used instead of a semiconductor package of the QFP type disclosed in Japanese Patent Laid-Open No. 8-340161. Accordingly, the following configuration with regard to electrode terminals connected to the bus wirings is more frequently used. That is, the bus wirings are connected to not only the electrode terminals arranged on an outermost circumference of the semiconductor package but also the electrode terminals arranged on an inner circumference of the semiconductor package. It is therefore difficult to arrange the bus wirings at equal distances.
When the number of bus wirings is increased in the case of the multi-layered printed wiring board, the number of the via holes prepared in the ground layer or the power supply layer of the signal wirings is increased, and it is difficult to secure the return path for the signal. As described in Japanese Patent Laid-Open No. 8-340161, even when the via holes are prepared in a diagonal manner, the area for preparing the via holes is enlarged, and a degree of freedom for the board design is largely impaired. That is, if the via holes are prepared in a diagonal manner, the area for mounting electronic components such as bypass capacitors is limited, and the area for forming the other signal wirings is also limited.